The clocked evaluation at the file the channel hands over #
A program that lays its file puts the registers at consecutive addresses, each
one bit above the last. This file prices the clocked evaluation at the file the
register channel hands over instead, where the registers are the cells the
channel writes and a step of a walk across the file can cost as much as the whole
file (DescriptiveComplexity.Draw.Data.nexIxEvalB_regLaid_reachesIn).
The four widths are regW, regWP, regWR, regWK
(DescriptiveComplexity.Draw.Data.regW and its neighbors), each bounded by
one number, regWidthBound: three of the four are linear in the file's own
bound, and the seek is quadratic, being a pass of the file per bit of its
target.
One number above the register file's four widths #
One number above all four widths of the handed file: the file's bound and the walk across it, squared, with room for the constants.
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The register file's widths, under one number: the bound every address of the file is under, and the number of registers.
Equations
- dt.regWidthBd A R' P' = DescriptiveComplexity.Draw.Data.regWidthBound (Nat.card dt.RegIx) dt.regBound
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The two bridges at the handed file #
DescriptiveComplexity.Draw.Data.passEnc_regLaid and gateEnc_regLaid
discharge the gates' bridges at the file the channel hands over. The generic
lemmas they come from ask only that the registers stand for distinct elements,
that the layout order is linear, and that a register's block and tuple are its
element's – all of which the handed file has.
The inner gates' bridge at the handed file: hpassEnc, discharged.
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The gates' bridge at the handed file: hgateEnc, discharged.
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The evaluation itself #
The handed file's index at the clocked phases.
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The element a register stands for: itself.
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The handed file's four widths, at the clocked phases.
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The handed file's four widths, at the clocked phases.
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The handed file's four widths, at the clocked phases.
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The handed file's four widths, at the clocked phases.
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Distinct registers stand for distinct elements.
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The clocked evaluation at the handed file: the walk-back the opening's
dispatch owes, the branched spine over the spine's positions, and the exit into
the accepting phase, charged the handed file's own widths. This is
DescriptiveComplexity.Draw.Data.nexIxEvalB_reachesIn with every coherence of
the register channel's file discharged; what is left is the program's own, and
what the reduction still owes is its marking – the arguments, one element
below them, and nothing else.
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The thread, and the run from the sentence alone #
The packs at the handed file, built: the conditioned family the branched
thread takes as a parameter, from the gates' bridge and the inner gates'
(gateEnc_regLaid, passEnc_regLaid) rather than assumed.
Equations
- dt.regGatedSem h hord hzo mV w j st hg p a hp b = dt.ixGatedSem (DescriptiveComplexity.Draw.Data.regLaid h hord) ⋯ ⋯ hzo h mV j st hg p a hp b