The clocked evaluation at the file the channel hands over #
A program that lays its file puts the registers at consecutive addresses, each
one bit above the last. This file prices the clocked evaluation at the file the
register channel hands over instead, where the registers are the cells the
channel writes and a step of a walk across the file can cost as much as the whole
file (DescriptiveComplexity.Draw.Data.nexIxEvalB_regLaid_reachesIn).
The four widths are regW, regWP, regWR, regWK
(DescriptiveComplexity.Draw.Data.regW and its neighbors), each bounded by
one number, regWidthBound: three of the four are linear in the file's own
bound, and the seek is quadratic, being a pass of the file per bit of its
target.
One number above the register file's four widths #
One number above all four widths of the handed file: the file's bound and the walk across it, squared, with room for the constants.
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The width bound, as a power of two: at the file's own bound 2 ^ N and
its N registers, the widths are below 2 ^ (4 N + 14). Every clock argument
wants the widths as an exponent, and this is where the polynomial becomes
one.
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The register file's widths, under one number: the bound every address of the file is under, and the number of registers.
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- dt.regWidthBd A R' P' = DescriptiveComplexity.Draw.Data.regWidthBound (Nat.card dt.RegIx) dt.regBound
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The tower's costs at the handed file are polynomial in one number: the
IxWidthBd of DescriptiveComplexity.Draw.Data.ixLegWidth_le, at the four
widths the register channel's file is charged; what an instantiation owes of
the clock is again q ^ 25 ≤ 2 ^ (k · m).
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The file's widths, under a power of two of its register count: the file
bounds every address by 2 ^ N at N registers, and the widths are quadratic in
that. This is the first of the two places the clock's exponent comes from – the
other is the record's own dimensions.
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The evaluation's width at the handed file is polynomial in one number:
DescriptiveComplexity.Draw.Data.ixEvalWidth_le at ixWidthBd_regLaid. This
is the a of the clock – what one round of the evaluation costs – and what an
instantiation owes is q ^ 26 ≤ 2 ^ (k · m).
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The evaluation's width, as a power of two: ixEvalWidth_le_regLaid read
against the clock, which compares with 2 ^ (k · m) and not with a
polynomial. A number is below the next power of two above it
(Nat.lt_pow_succ_log_self), so twenty-six of them are below its twenty-sixth,
and that is the exponent w a reduction hands the clock.
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The dimensions that do not depend on the instance: the tag and formula budgets, the number of variables, and the atom, gate, argument and arity counts. They are the kernel's own, so a clock's exponent carries them as an additive constant.
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One number dominating every dimension the width bound compares against:
the pass widths, the two tuple counts, and the kernel's own dimensions
(dimC). It is a maximum and nothing else, so each of the ten comparisons
ixEvalWidth_le_regLaid asks for is one le_max away.
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The evaluation's width at the handed file, with nothing to discharge:
ixEvalWidth_le_two_pow_regLaid at evalQ, whose ten comparisons hold by
construction. This is the w of the clock, and it mentions the record alone.
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The two bridges at the handed file #
DescriptiveComplexity.Draw.Data.passEnc_regLaid and gateEnc_regLaid
discharge the gates' bridges at the file the channel hands over. The generic
lemmas they come from ask only that the registers stand for distinct elements,
that the layout order is linear, and that a register's block and tuple are its
element's – all of which the handed file has.
The inner gates' bridge at the handed file: hpassEnc, discharged.
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The gates' bridge at the handed file: hgateEnc, discharged.
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The evaluation itself #
The handed file's index at the clocked phases.
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The element a register stands for: itself.
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The handed file's four widths, at the clocked phases.
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The handed file's four widths, at the clocked phases.
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The handed file's four widths, at the clocked phases.
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The handed file's four widths, at the clocked phases.
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Distinct registers stand for distinct elements.
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The clocked evaluation at the handed file: the walk-back the opening's
dispatch owes, the branched spine over the spine's positions, and the exit into
the accepting phase, charged the handed file's own widths. This is
DescriptiveComplexity.Draw.Data.nexIxEvalB_reachesIn with every coherence of
the register channel's file discharged; what is left is the program's own, and
what the reduction still owes is its marking – the arguments, one element
below them, and nothing else.
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The clocked evaluation at the handed file, whatever the verdict:
nexIxEvalB_regLaid_reachesIn with the verdict not assumed
(nexIxEvalOutB_any_reachesIn).
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The thread, and the run from the sentence alone #
The packs at the handed file, built: the conditioned family the branched
thread takes as a parameter, from the gates' bridge and the inner gates'
(gateEnc_regLaid, passEnc_regLaid) rather than assumed.
Equations
- dt.regGatedSem h hord hzo mV w j st hg p a hp b = dt.ixGatedSem (DescriptiveComplexity.Draw.Data.regLaid h hord) ⋯ ⋯ hzo h mV j st hg p a hp b
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The clocked evaluation at the handed file, with its thread: the same run
as nexIxEvalB_regLaid_reachesIn with the tape and control families
constructed – the branched thread at the packs the bridges build – so that a
program has only to name the state it enters the evaluation in.
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The clocked evaluation at the handed file, with its thread, whatever the
verdict: the same run
as nexIxEvalB_regLaid_reachesIn with the tape and control families
constructed – the branched thread at the packs the bridges build – so that a
program has only to name the state it enters the evaluation in.
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The clocked evaluation at the handed file, from the sentence alone: the
run above with the output's leg discharged. The output variable is nullary, so
everything its leg asks about argument blocks is vacuous – there are none – and
the one thing left is its verdict, which ixOutAcc_iff_out reads as the
expansion's output sentence at the stage the tracks hold. So what a program has
to bring to its own evaluation is the entry state, the enumeration, the stage
its guess wrote, and the sentence being true.
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The clocked evaluation at the handed file, and the verdict it leaves:
the run above with the sentence not assumed, and the accepting bit read as
what it is – the sentence's own value (ixOutAcc_iff_out). A backward reading
uses this: the run exists whatever the verdict, and the bit says which.